A circuit for biasing the differential-to-CMOS level converter is provided for ensuring that signal transitions are detectable at a proper threshold. The objects, features and advantages of the present invention will be apparent from the following detailed description in which:.
A method and apparatus are described for the conversion of small amplitude differential serial data transmission signals to single-ended digital CMOS level signals. In the following description, many specific details are set forth such as relative voltage levels, etc. It will be apparent, however, to one of ordinary skill in the art that the present invention may be practiced without such specific details. In other instances, well-known structures and techniques have not been described in detail in order not to obscure unnecessarily the present invention.
The preferred embodiment of the present invention is intended to be incorporated into a data bus receiving module for use in a data communication system where information is transmitted in serial format at a very high rate of speed. Particularly, the preferred embodiment of the present invention is intended to be incorporated in a data communication system complying with IEEE Standard "High Performance Serial Bus" wherein data is transmitted over a twisted-pair cable from a transmitter on one node to a receiver on another node.
However, those of ordinary skill in the art will see that the present invention may be implemented in a wider field of use. In light of the reasons discussed in the previous section, it can be seen that it is desirable in high speed serial transmission systems to use differential signals to advantageously limit pulse-width distortion and to reduce other negative effects that are present when transmitting single-ended signals. The signal receiver circuit of FIG. Stage A comprises a front end fully differential low offset amplifier 2.
The front end amplifier 2 provides good common mode range and common mode rejection with a differential output level of around MV peak-to-peak. Stage B in FIG. The linear amplifier 3 should provide gain of only 1 to 1. Linear amplifier 3 should also provide equal rise and fall times for the output signals A and B. Stages C, D and E comprise the preferred embodiment of the present invention which receive a differential input signal having a common mode voltage near the Vcc supply rail and approximately equal rise and fall times.
Stage C comprises level shifting circuitry which provides a differential to single-ended gain of about 1. Stage C's single-ended output also provides good matching between its output rise and fall times. Stage D comprises amplifier circuitry 15 which amplifies the stage C output to CMOS levels while also providing fast edges and good rise and fall time matching. Finally, stage E comprises biasing circuitry 10 for biasing stage D at the optimum bias that provides for the least timing distortion best match in rise and fall time.
Biasing stage E also makes the overall circuit's performance independent of process, temperature and power supply. The differential signal received by the level-shifting with gain stage 5 is the output from the linear amplifier circuit 3 stage B.
The A and B signals received by stage C have those characteristics described above, that is, approximately equal rise and fall times with a common mode voltage near the power supply rail. This type of circuit acts to match the rise and fall times of its outputs and is therefore very useful for minimizing timing distortion.
At the same time this circuit provides a useful common mode level shift necessary to bias the next stage while providing gain and having high bandwidth. Differential signal constituents A and B are received by the level-shifting stage 5 with signal A being coupled to the gate of n-channel transistor 25 and signal B being supplied to the gate of n-channel transistor The level shifter with gain circuit 5 further includes n-channel transistors 27 and Transistor 27 has its drain coupled to the source of transistor 25 and its source coupled to ground.
N-channel transistor 28 has its drain coupled to the source of transistor 26 and its source coupled to ground. This transistor arrangement is further cross-coupled with the gate of n-channel transistor 28 being coupled to the source of transistor 25 and drain of transistor 27, while the gate of n-channel transistor 27 is coupled to the drain of transistor 28 and the source of transistor The way in which the cross coupled circuit matches the rise and fall times can be understood by first looking at the performance of a non-cross coupled NMOS level shift circuit shown in FIG.
As signal A rises so does signal C and it rises fairly rapidly since the current in transistor 51 is increased due to charging of capacitance attached to node C. As signal A rises signal B falls since its a differential input this causes signal D to fall but it falls more slowly than C rises since the current in transistor 52 is decreased due to discharge of capacitance at node D.
This assumes that all transistors are biased in their active region and that transistors 53 and 54 act as current sources biased by Vbias reference voltage. Referring back now to FIG. As signal A rises signal C would like to rise quickly and so strongly increases the current in source transistor 28 thus speeding up the fall in signal D which otherwise would fall slowly. Now signal D will help speed up the rise in signal C by reducing the current in transistor 27 but since it wants to be slower it does less to speed up the signal C rise time than signal C does to speed up signal D's fall time; this process tends to match the rise and fall time of signal D and C by speeding up the fall time more than speeding up the rise time.
The gain of the cross coupled circuit is controlled by the size ratio between Wt width of the top transistors and Wb width of the bottom transistors. Note that it is assumed that the channel lengths are equal. Note that in this embodiment the transistors 25 and 26 are shown body connected to minimize attenuation due to body effect.
Typical signal waveforms are shown in FIG. The input signals A and B swing between 4. The output signal D is inverted with respect to A minus B differential input signal and is 1.
The common mode of the output is the common mode voltage at the input less than Vgs drop of the top transistors and is typically 2. The amplifier stage 10 of the present invention is illustrated in FIG. The signal coming from node D is input to the gates of the two transistors 30 and P-channel transistor 30 has its source coupled to the 5 volt power supply while n-channel transistor 31 has its source coupled to ground.
The CMOS transistors 30 and 31 are optimally utilized with the p-channel transistor having twice the channel width of the n-channel transistor giving transistor 30 approximately the same strength as transistor There is also shown in FIG.
In docs folder you can find an Application Note on conversion circuit In reference design folder you can find an Altium Design project as a reference design for Single Ended to Differential conversion for R device. Skip to content.
Star 0. Branches Tags. Could not load branches. Could not load tags. Latest commit. Git stats 3 commits. Output section can have the same general configuration as that shown as in FIG. For purposes of clarity, many of the details of the embodiments that are widely known and are not relevant to the present invention have been omitted from the following description. Furthermore, the particular features, structures or characteristics may be combined as suitable in one or more embodiments of the invention.
It is understood that the embodiments of the invention may be practiced in the absence of an element and or step not specifically disclosed. That is, an inventive feature of the invention can be elimination of an element. Similarly, it should be appreciated that in the foregoing description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure aiding in the understanding of one or more of the various inventive aspects.
This method of disclosure, however, is not to be interpreted as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim.
Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment.
Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this invention. A differential-to-single ended converter circuit, comprising: an input section that includes: an input differential transistor pair including a first input transistor having a control terminal coupled to a first differential input and a controllable impedance path coupled to a first detect node, and a second input transistor having a control terminal coupled to a second differential input and a controllable impedance path coupled to a second detect node;.
The differential-to-single ended converter circuit of claim 1 , wherein: the controllable impedance path of the first input transistor is coupled in series with the controllable impedance path of the first latch transistor; and. The differential-to-single ended converter circuit of claim 1 , wherein: the controllable impedance path of the first input transistor is coupled in parallel with the controllable impedance path of the first latch transistor; and.
The differential-to-single ended converter circuit of claim 1 , wherein: the first input transistor, second input transistor, first latch transistor, and second latch transistor comprise transistors of the same conductivity type.
The differential-to-single ended converter circuit of claim 1 , wherein: the first latch transistor and second latch transistor are selected from a group consisting of n-channel insulated gate field effect transistors IGFETs and p-channel IGFETs.
The differential-to-single ended converter circuit of claim 1 , wherein: the first and second latch transistors are selected from a group consisting of insulated gate field effect transistors, bipolar transistors: and junction field effect transistors. The differential-to-single ended converter circuit of claim 1 , further including: a first output transistor having a controllable impedance path coupled between the output node and the first power supply node, and a control terminal coupled to the first detect node.
The differential-to-single ended converter circuit of claim 7 , further comprising: a load circuit having a first load impedance coupled between the second power supply node and the controllable impedance path of the first output transistor. The differential-to-single ended converter circuit of claim 8 , wherein the load circuit includes a current mirror circuit comprising: a first mirror transistor with a controllable impedance path coupled between the output node and the second power supply node,.
The differential-to-single ended converter circuit of claim 1 , further including: a first detect load device that provides an impedance between the first detect node and the first power supply node; and. The differential-to-single ended converter circuit of claim 10 , wherein: the first detect load device and second detect load device both comprise transistors having control terminals coupled to their respective controllable impedance paths. The differential-to-single ended converter circuit of claim 1 , further comprising: a plurality of delay stages arranged in series with one another including an output delay stage that outputs a dual signal differential voltage as inputs to the first and second differential inputs.
The differential-to-single ended converter circuit of claim 12 , wherein: the plurality of delay stages are coupled in a ring to form a ring oscillator, at least one delay stage having a delay controlled according to a control voltage; and.
The differential-to-single ended converter circuit of claim 1 , further including: a first current source coupled between the second power supply node and the controllable impedance path of the first input transistor; and. USP true USB1 en. USB2 en. USA en. Digital-to-analog converter with current source transistors operated accurately at different current densities. Method of and an arrangement in a telecommunication system for regulating the phase position of a controlled signal in relation to a reference signal.
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System development and debug tools for power management functions in a computer system. Magnetic disk storage apparatus with phase sync circuit having controllable response characteristics. Systems utilizing a single chip microcontroller having non-volatile memory devices and power devices. Apparatus for reducing jitter of a spectrum spread clock signal and method therefor.
Microcomputer free from control of central processing unit CPU for receiving and writing instructions into memory independent of and during execution of CPU. Supervisory control system for networked multimedia workstations that provides reconfiguration of workstations by remotely updating the operating system.
Safe and low cost computer peripherals with force feedback for consumer applications. Intelligent real-time graphic-object to database linking-actuator for enabling intuitive on-screen changes and control of system configuration. Multiprocessing system employing an adaptive interrupt mapping mechanism and method. User-directed method for operating on an object-based model data structure through a second contextual image. Microcontroller with security logic circuit which prevents reading of internal memory by external program.
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System and method for creating and validating structural description of electronic system from higher-level and behavior-oriented description. Tile-based modular routing resources for high density programmable logic device.
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Method and system for designing and analyzing optical application specific integrated circuits. Method and system for creating and verifying structural logic model of electronic design from behavioral description, including generation of logic and timing models.
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System for writing a plurality of data bits less than from the total number of bits in a data register using a single register write operation. Circuitry for providing external access to signals that are internal to an integrated circuit chip package.
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Chain-connected shift register and programmable logic circuit whose logic function is changeable in real time.
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